Nvidia Unveils Proprietary NVHBM Memory, Limited to NVLink Fusion Partners

Nvidia has announced a new generation of high-bandwidth memory called NVHBM, designed in-house rather than relying on standard HBM4E chips supplied by SK hynix, Samsung, or Micron. The company makes no secret that access to the technology will be tightly restricted, reserved solely for partners in its NVLink Fusion program.

What Nvidia unveiled

The key change in NVHBM is moving the memory controller off the main XPU compute chip and directly into the base layer of the HBM stack. In the standard JEDEC approach, the controller occupies part of the compute chip's die area and communicates with memory over a wide parallel interface. Nvidia replaces it with a narrower, serial link, shrinking the interface footprint by roughly two-thirds.

The freed-up silicon can be used for additional matrix units, SRAM cache, or circuits tailored to specific AI workloads. The company says the end result is a chip that is faster, more power-efficient, and architecturally more flexible than competing designs built around off-the-shelf HBM4E dies.

Why access is restricted

NVHBM will not reach the open market as a component any accelerator maker can simply order from a memory supplier. Distribution runs exclusively through the NVLink Fusion program, under which Nvidia licenses select partners to integrate their own XPU and CPU designs with its rack-scale platform. That means companies building custom accelerators must partner with Nvidia to gain access to the new memory rather than purchasing it as an off-the-shelf part.

The first partner named is Annapurna Labs, the Israeli company owned by Amazon that develops the Trainium processors. The two companies will jointly work on integrating NVHBM into the NVLink scale-up architecture, supporting the next generation of Trainium4 chips paired with Nvidia processors. Amazon has not yet disclosed exactly which chip will debut the technology.

NVHBM represents a new architectural approach to advancing high-bandwidth memory - Nafea Bshara, Annapurna Labs (Amazon)

Market context

The idea of custom HBM memory with a relocated controller is not entirely new. Marvell showed a similar concept back in December 2024, working with Micron, Samsung, and SK hynix. Nvidia's edge, then, lies not in the technical innovation itself but in the scale of deployment and control over distribution that its leading position in the AI accelerator market affords it.

The move fits a broader trend of the biggest players moving away from HBM memory bought as a ready-made component toward solutions engineered for a specific architecture. For memory suppliers such as SK hynix or Samsung, this shifts their role from providers of a standard chip to technology partners dependent on specifications dictated by accelerator makers.

What this means for the market

For cloud companies and hyperscalers building their own AI accelerators, the message is clear: access to Nvidia's most energy-efficient and fastest memory requires entering a formal NVLink Fusion partnership, not just signing a purchase agreement. This deepens smaller chip designers' dependence on Nvidia's goodwill and could widen the lead held by companies that already have close ties with it, such as Amazon.

For Polish companies and institutions involved in AI infrastructure projects, including the planned AI gigafactories, limited access to NVHBM means that the most advanced power and performance figures will remain the domain of a handful of major players rather than a standard feature available to every hardware integrator.

Nvidia has not yet given a specific date for the first commercial deployments, pointing only to the start of mass production in 2027. In the meantime, the industry will be watching whether more partners join the NVLink Fusion program, and how independent memory suppliers respond to a model that leaves them with less control over their own product.