Korean Researchers Quadruple Memory Density for AI Chips

A team from South Korea's POSTECH university has developed a method for stacking more than ten ultra-thin silicon layers, achieving a memory packing density roughly four times higher than in today's commercial HBM memory chips. The results were published on July 8, 2026, in the journal Results in Engineering.

High bandwidth memory, known as HBM, is today one of the key bottlenecks in hardware used to train and run large language models. The more memory layers that can be packed into a single module, the more data a GPU can process simultaneously without waiting for it to be transferred from external chips. The problem is that the thinner and more numerous the layers, the harder it becomes to stack and electrically connect them precisely without damage.

Two processes in one step

The POSTECH team solved this problem by merging two production stages into one. Instead of first precisely stacking thin silicon layers and then separately connecting them electrically, the researchers developed a transfer printing method combined with the simultaneous formation of metallic connections at the moment each layer touches the previous one. The bonding relies on copper-tin diffusion bonding carried out at low temperature and low pressure, which limits warping of the paper-thin layers as the stack grows.

By achieving an integration density approximately four times higher than existing HBM technologies, we expect this technology to become - Prof. Seok Kim, POSTECH

Still a lab, not a fab

The study's authors are clear that the achievement is, for now, a laboratory result. It remains unclear whether the method can be transferred to industrial-scale production lines, where what matters is not just packing density but also process repeatability across millions of units. HBM memory makers such as SK Hynix and Samsung have for years been investing in competing approaches to increasing the number of layers in their modules.

Why it matters for AI

Demand for HBM memory keeps growing with each new generation of AI graphics chips. Analysts estimate that AI data centers already account for the majority of global consumption of advanced memory chips, and manufacturers have for months been signaling limited production capacity. If the method developed in Pohang proves scalable, it could give memory makers a new way to increase module capacity without waiting for the next generation of lithography.

For the Polish market, where companies and universities are increasingly investing in local AI computing infrastructure, the price and availability of HBM memory has a direct impact on the cost of building in-house clusters. Any breakthrough that increases memory density while keeping production costs reasonable could, over the longer term, lower the entry barrier for smaller players planning their own computing installations.

The researchers say they plan further work on moving the technology beyond laboratory conditions. The key test will be whether the method can be reproduced at larger production scale and whether the process costs prove competitive with techniques already used by major memory manufacturers.

Sources: Tech Xplore (techxplore.com), chip.pl